Due to large address spaces supported by modern processors, a traditional level 1 (L1) tag lookup involves a comparison encompassing a large number of bits. To address the power consumed by the wide comparators need for traditional L1 cache tag lookup, traditional cache tags have been replaced with a vector pointing to an entry in a fully associative translation lookaside buffer (TLB). This configuration, however, constrains the size of the TLB and results in undesirably frequent TLB misses.